To advance the field of electronics prognostics, the study of transistor fault modes and their precursors is essential. The objective is to focus on a platform for the aging, characterization, and scenario simulation of gate controlled power transistors. The platform supports thermal cycling, dielectric over-voltage, acute/chronic thermal stress, current overstress and application specific scenario simulation. In addition, the platform supports in-situ transistor state monitoring, including measurements of the steady-state voltages and currents, measurements of electrical transient response, measurement of thermal transients, and extrapolated semiconductor impedances, all conducted at varying gate and drain voltage levels. The aging and characterization platform consists of an acquisition and aging hardware system, an agile software architecture for experiment control and a collection of industry developed test equipment.
Thermal stress and electrical stress are the most common aging methodologies. Thermal cycling and chronic temperature overstress are prevalent thermal stress methods, with thermal cycling among the most prevalent accelerated aging methodology in electronics. Thermal cycling subjects devices to rapid changes in temperature differentials causing thermal expansion and contraction. Die solder degradation and wire lift are associated strongly with this aging method. Previous experiments on Metal-Oxide-Semiconductor FETs (MOSFETs) cycled 7000 times from -50°C to 100°C resulted in void formation in over 30% of the die solder attachment. Similar results were demonstrated in IGBTs under power cycling with wire lift also occurring. It should be noted that this effect is solder dependent, with lead-free packages showing better resistance to solder degradation. Thermal overstress, another prevalent method, subjects devices to high temperatures for extended periods of time. TDDB is accelerated under high temperatures and transistors have exhibited temperature dependant lifetimes accelerated by this mechanism. IGBTs aged with self heating have shown changes in current ringing characteristics during switching.
Electrical overstress can be induced though transient and steady-state methods. Transient methods include electro static discharge (ESD), inductive switching and electromagnetic pulses. ESD is a leading cause of gate oxide failure and hard switching of inductive loads, causes voltage spikes which can cause significant damage to drain-source junctions. One can distinguish between thermally induced failure mechanisms (contact metal burnout, fused metallization), and electric field induced damage. Steady-state methods include chronic over-voltage and over-current. Applying high gate voltages, setting gate voltage (Vg) to maximize drain current, and applying current overstress across the drain have been shown to induce hot carrier and TBBD. Fault precursors that could be monitored, amongst others, appear as collector-emitter leakage, gate leakage, changes in gm and shifts in Vgth.
This section describes the design and implementation of a system capable of performing accelerated aging tests, application simulations and device characterization on gate controlled power transistors to induce and analyze fault precursors. The proposed system should have the ability to act as test bed for the validation of prognostic algorithms for power transistors. System requirements relevant to these goals are:
Transistor Gate Hardware - Arbitrary signal generation is required over the full voltage range of a transistor gate for the support of robust scenario simulation and characterization. A review of industry datasheets yields rise and fall times on the order of 10ns and 50ns, for the specified class of MOSFETS and IGBTs. Gate voltages are limited to a 20V maximum for both transistors. A driver that exceeds this maximum would be useful for hot carrier injection and TDDB aging scenarios. Slew rates in excess of 2V/ns are desired for fast large signal swings. Gate capacitances for specified transistors are typically in the range of 500pF for MOSFETs and 6nF for IGBTs, requiring a powerful gate driver. The necessity for arbitrary signal generation at the transistor gate suggests the use of a linear amplifier. A driver bandwidth in excess of 100MHz is desired. Additional equipment with higher performance or special functionality may need access to the transistor gate. Therefore, the gate circuit should incorporate a switching mechanism between various instruments. A switching network for the electrical isolation of the gate should also be implemented where leakage or high voltages may cause problems.
Load and Power Supply Hardware - It is desirable to accommodate load currents from 10A up to 100A. Contacts and Printed Circuit Board (PCB) components must be rated for high amperages. Power supplies voltages should be programmable to accommodate dynamic scenarios. Power conditioning is desired to reduce interference from power supply feedback circuits or power cable inductance. Dynamic loads are desirable for the emulation of rich system scenarios.
Hardware Electrical Signal Acquisition - The transient response of voltage and current signals corresponding to the gate-emitter and the collector-emitter nodes should be measured in-situ. Transient acquisition rates greater than 1ns are desirable and bandwidths in excess of 300MHz are required to measure rise and fall times. PCB design must take transients into consideration. Overlap between collector and emitter traces should be minimized to reduce parasitic capacitance that may change transient characteristics. Traces should be kept very short or be impedance matched to prevent signal reflection. If possible, instrumentation amplifiers should be used for isolation and common mode rejection. Low-pass filtered transistor signals should also be measured. These averaged signals are especially important for SMPS (Switch Mode Power Supply) applications. Power management ICs (Integrated Circuits) in SMPS already implements voltage monitors, making them an ideal candidate for future prognostic implementations.
Hardware Thermal Environment - Controlling thermal environment is important for transistor characterization as their characteristics are heavily temperature dependant. Datasheets reveal Vgth shifts on the order of -10mV/°C. Collector-emitter resistances will often change by an order of magnitude over a 100°C differential. Such shifts must not be attributed to changes in the intrinsic characteristics of the transistor. In addition, aging and simulation scenarios involve extreme environmental conditions. The system should allow temperatures ranging from far below 0°C to above 300°C, where IGBTs have shown short-term operability. Internal junction temperature measurements, often measured using Vgth, can be problematic as hot carrier effect also acts on Vgth. Special effort should be taken to measure silicon die, package epoxy and package heat sink temperatures using thermal methods, in order to enable accurate temperature control and thermal impedance degradation measurements.
Software Control and Data Acquisition-The chosen software development environment must support communication with multiple hardware devices, act as an in-the-loop feedback controller, and save gigabytes of data collected over long test runs. The test software must perform a multitude of different experiments related to scenario generation and transistor characteristics. It should interact easily with the user and display results in real-time.
Software Architecture - The software framework controlling the system should enable a dynamic and scalable development environment. Scientific software development is usually iterative, where results dictate new and novel experiments. Equipment upgrades will require system adaptation. A thorough consideration of software engineering principles is crucial to the development of a successful software package.