Wednesday, June 29 Technical Posters Session (5:20-7:30)
J.L.M Amaral,  R. Tanscheit, J.F.M Amaral, M. Pacheco, and A. Mesquita Tuning Evolvable PID Controllers through a Clonal Selection Algorithm
Shivakumar Viswanathan and Jordan B. Pollack On the Robustness Achievable with Stochastic Development Process
Shuguang Zhao, Licheng Jiao, and Yuping Wang Evolutionary Design of Analog Circuits with a Uniform Design Based Multi-Objective Adaptive Genetic Algorithm
Heng Liu, Julian F. Miller, and Andy M. Tyrrel Intrinsic Evolvable Hardware Implementation of a Robust Biological Development Model for Digital Systems
A.P. Shanthi, L. Karthik Singaram, and Ranjani Parthasarathi Evolution of Asynchronous Sequential Circuits
John C. Gallagher, Sanjay K. Boddhu, and Saranyan Vigraham A Reconfigurable Continuous Time Recurrent Neural Network for Evolvable Hardware Applications
Phillip Moore, Ganesh K. Venayagamoorthy, and Gaurav Singhal Evolving Combinational Logic Circuits Using a Hybrid Quantum Evolution and Particle Swarm Inspired Algorithm
Nicholas J. Macias and Lisa J. K. Durbeck A Hardware Implementation of the Cell Matrix Self-Configurable Architecture: The Cell Matrix MOD 88
Garrison W. Greenwood Practical Concerns When Evolving Circuits Impervious to Antecipated Faults
Andre Stauffer, Daniel Mange,  and Gianluca Tempesti Embryonic machines that grow, self-replicate and self-repair
A. Hariri, R. Rastegar, K. Navi, M. Zamani, and M. R. Meybodi Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution
He Jingsong, Wang Xufa, Zhang Min, Wang Jiying, Fang Qiansheng New Research on Scalability of Lossless Image Compression by GP Engine
John Rieffel and Jordan Pollack Evolving Assembly Plans for Fully Automated Design and Assembly
Nasri Sulaiman and Tughrul Arslan A Multi-objective Genetic Algorithm for On-chip Real-time Optimisation of Word Length and Power Consumption in a Pipelined FFT Processor targeting on MC-CDMA Receiver