An aging system for power semiconductors that isolates electrical overstress from temperature overstress has been built. The system controls the internal temperature of the test article in order to avoid exciting other failure mechanisms related to the packaging of the device. This system will provide a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide health management solutions for these types of devices.
Some failure mechanisms of power transistors are related to the packaging of the devices, particularly due to mechanical stresses from thermal cycling. Thermal cycling, as an aging methodology, is regularly used to accelerate the aging of the devices by cycling between temperatures considerably larger than those seen in normal operation. The advantage of the isothermal aging system is that it allows for precise control of internal temperatures, facilitating the exploration of intrinsic failure mechanisms not related to the packaging. Intrinsic failure mechanisms are related to the semiconductor and gate structures. Particularly, these are changes to the semiconductor doping and gate oxide (dielectric) damage. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only. This is representative of the way these devices operate in real-world applications and is the methodology used to assess reliability.
Temperature is controlled by active thermal-electric units that are driven using physical models of the thermal process of the devices in a TO-220 package. Several electrical signals, as well as temperatures, are measured in situ and recorded for further analysis in the identification of leading failure indicators.
BACKGROUND: Failure of electronic devices is a concern for newer aircraft, which will see an increased use of electronics to drive and control safety-critical equipment throughout the aircraft. This effort – as part of the IVHM project – investigates whether precursors to failure in electronics can be found and how one would predict the remaining life of electronic components. Gate-controlled power transistors, like the power MOSFETs (metal-oxide-semiconductor-field-effect-transistor) and the IGBTs (insulated-gate bipolar transistor), are power semiconductor devices that are employed in a variety of switch mode power supplies and electrical motor drivers where high frequency switching of high power signals is required. The electronics prognostics effort in the Diagnostics and Prognostics Group/Prognostics Center of Excellence currently focuses on identification of failure mechanisms and the development of accelerated aging methodologies and systems to accelerate the aging process of test devices while continuously measuring key electrical and thermal parameters. Accelerated aging systems allow for the understanding of the effects of failure mechanisms and the identification of leading indicators of failure, which are essential in the development of physics-based degradation models and the prediction of remaining useful life.
COLLABORATORS: Jose Celaya (SGT), Phil Wysocki (ASRP), Sankalita Saha (MCT), Abhinav Saxena (SGT ), Trevor Hutchins (USRP), Mona Fahimi (EAP), and Vladislav Vashchenko (SGT)
NASA PROGRAM FUNDING: Aviation Safety and IVHM
Contact: Jose R. Celayas